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CACM
2010
179views more  CACM 2010»
13 years 7 months ago
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Exploiting the multiprocessors that have recently become ubiquitous requires high-performance and reliable concurrent systems code, for concurrent data structures, operating syste...
Peter Sewell, Susmit Sarkar, Scott Owens, Francesc...
CGO
2009
IEEE
14 years 1 months ago
Reducing Memory Ordering Overheads in Software Transactional Memory
—Most research into high-performance software transactional memory (STM) assumes that transactions will run on a processor with a relatively strict memory model, such as Total St...
Michael F. Spear, Maged M. Michael, Michael L. Sco...
CASES
2009
ACM
13 years 10 months ago
A case study of on-chip sensor network in multiprocessor system-on-chip
Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system-on-chip (MPSoC) to satisfy the increasing demands of applic...
Yu Wang 0002, Jiang Xu, Shengxi Huang, Weichen Liu...
QOSA
2010
Springer
13 years 10 months ago
Parameterized Reliability Prediction for Component-Based Software Architectures
Critical properties of software systems, such as reliability, should be considered early in the development, when they can govern crucial architectural design decisions. A number o...
Franz Brosch, Heiko Koziolek, Barbora Buhnova, Ral...
JSS
2008
91views more  JSS 2008»
13 years 7 months ago
Software architecture reliability analysis using failure scenarios
We propose an approach for analyzing software architectures with respect to reliability to improve fault tolerance. The approach defines a failure scenario model that is based on ...
Bedir Tekinerdogan, Hasan Sözer, Mehmet Aksit