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ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
14 years 4 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
MEMOCODE
2007
IEEE
14 years 4 months ago
Scheduling as Rule Composition
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
Nirav Dave, Arvind, Michael Pellauer
QEST
2007
IEEE
14 years 4 months ago
A Productivity Centered Tools Framework for Application Performance Tuning
Our productivity centered performance tuning framework for HPC applications comprises of three main components: (1) a versatile source code, performance metrics, and performance d...
Hui-Fang Wen, Simone Sbaraglia, Seetharami Seelam,...
DAMON
2007
Springer
14 years 4 months ago
Vectorized data processing on the cell broadband engine
In this work, we research the suitability of the Cell Broadband Engine for database processing. We start by outlining the main architectural features of Cell and use microbenchmar...
Sándor Héman, Niels Nes, Marcin Zuko...
IEAAIE
2007
Springer
14 years 4 months ago
Generating Cartoon-Style Summary of Daily Life with Multimedia Mobile Devices
Mobile devices are treasure boxes of personal information containing user’s context, personal schedule, diary, short messages, photos, and videos. Also, user’s usage informatio...
Sung-Bae Cho, Kyung-Joong Kim, Keum-Sung Hwang