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» The Logic of Large Enough
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FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
14 years 14 days ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
ICDT
2010
ACM
147views Database» more  ICDT 2010»
14 years 6 days ago
Querying Parse Trees of Stochastic Context-Free Grammars
Stochastic context-free grammars (SCFGs) have long been recognized as useful for a large variety of tasks including natural language processing, morphological parsing, speech reco...
Sara Cohen, Benny Kimelfeld
ASPDAC
2005
ACM
93views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Power minimization for dynamic PLAs
—Dynamic programmable logic arrays (PLAs) which are built of the NOR–NOR structure, have been very popular in high performance design because of their high-speed and predictabl...
Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, ...
SIGCOMM
2010
ACM
13 years 9 months ago
Rethinking iBGP routing
The Internet is organized as a collection of administrative domains, known as Autonomous Systems (ASes). These ASes interact through the Border Gateway Protocol (BGP) that allows ...
Iuniana M. Oprescu, Mickael Meulle, Steve Uhlig, C...
CJ
2006
84views more  CJ 2006»
13 years 9 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope