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FPL
2008
Springer
86views Hardware» more  FPL 2008»
13 years 9 months ago
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Ha...
WWW
2009
ACM
14 years 8 months ago
Using graphics processors for high performance IR query processing
Web search engines are facing formidable performance challenges as they need to process thousands of queries per second over billions of documents. To deal with this heavy workloa...
Shuai Ding, Jinru He, Hao Yan, Torsten Suel
LCTRTS
2005
Springer
14 years 1 months ago
Generation of permutations for SIMD processors
Short vector (SIMD) instructions are useful in signal processing, multimedia, and scientific applications. They offer higher performance, lower energy consumption, and better res...
Alexei Kudriavtsev, Peter M. Kogge
NIPS
1992
13 years 8 months ago
Silicon Auditory Processors as Computer Peripherals
Several research groups are implementing analog integrated circuit models of biological auditory processing. The outputs of these circuit models have taken several forms, includin...
John Lazzaro, John Wawrzynek, Misha Mahowald, Mass...
INTEGRATION
2007
98views more  INTEGRATION 2007»
13 years 7 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...