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ASYNC
2002
IEEE
123views Hardware» more  ASYNC 2002»
14 years 21 days ago
Improving Smart Card Security Using Self-Timed Circuits
We demonstrate how 1-of-n encoded speed-independent circuits provide a good framework for constructing smart card functions that are resistant to side channel attacks and fault in...
Simon W. Moore, Robert D. Mullins, Paul A. Cunning...
IPPS
1999
IEEE
14 years 17 hour ago
Condition-Based Maintenance: Algorithms and Applications for Embedded High Performance Computing
Condition based maintenance (CBM) seeks to generate a design for a new ship wide CMB system that performs diagnoses and failure prediction on Navy shipboard machinery. Eventually, ...
Bonnie Holte Bennett, George D. Hadden
ASAP
1996
IEEE
96views Hardware» more  ASAP 1996»
13 years 12 months ago
Kestrel: A Programmable Array for Sequence Analysis
Kestrel is a programmable linear array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, ...
Jeffrey D. Hirschberg, Richard Hughey, Kevin Karpl...
DAGSTUHL
2007
13 years 9 months ago
Parallelism through Digital Circuit Design
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eï¬...
John O'Donnell
BMCBI
2008
108views more  BMCBI 2008»
13 years 7 months ago
SPRINT: A new parallel framework for R
Background: Microarray analysis allows the simultaneous measurement of thousands to millions of genes or sequences across tens to thousands of different samples. The analysis of t...
Jon Hill, Matthew Hambley, Thorsten Forster, Murie...