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ICS
1999
Tsinghua U.
14 years 7 hour ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
HPDC
2012
IEEE
11 years 10 months ago
Dynamic adaptive virtual core mapping to improve power, energy, and performance in multi-socket multicores
Consider a multithreaded parallel application running inside a multicore virtual machine context that is itself hosted on a multi-socket multicore physical machine. How should the...
Chang Bae, Lei Xia, Peter A. Dinda, John R. Lange
SOSP
1993
ACM
13 years 9 months ago
Protection Traps and Alternatives for Memory Management of an Object-Oriented Language
Many operating systems allow user programs to specify the protectionlevel (inaccessible, read-only, read-write) of pages in their virtual memory address space, and to handle any p...
Antony L. Hosking, J. Eliot B. Moss
ICS
2003
Tsinghua U.
14 years 28 days ago
Estimating cache misses and locality using stack distances
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
Calin Cascaval, David A. Padua
ASPLOS
2008
ACM
13 years 9 months ago
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
Michal Wegiel, Chandra Krintz