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ISCA
2009
IEEE
150views Hardware» more  ISCA 2009»
14 years 3 months ago
Stream chaining: exploiting multiple levels of correlation in data prefetching
Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetc...
Pedro Diaz, Marcelo Cintra
LCTRTS
2007
Springer
14 years 3 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
ICPP
2009
IEEE
13 years 6 months ago
A Resource Optimized Remote-Memory-Access Architecture for Low-latency Communication
This paper introduces a new highly optimized architecture for remote memory access (RMA). RMA, using put and get operations, is a one-sided communication function which amongst ot...
Mondrian Nüssle, Martin Scherer, Ulrich Br&uu...
USENIX
2001
13 years 10 months ago
Nickle: Language Principles and Pragmatics
Nickle is a vaguely C-like programming language for numerical applications, useful both as a desk calculator and as a prototyping and implementation language for numerical and sem...
Bart Massey, Keith Packard
IISWC
2008
IEEE
14 years 3 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood