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HOTI
2005
IEEE
14 years 2 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
MSWIM
2004
ACM
14 years 2 months ago
Speeding up the evaluation of multimedia streaming applications in MANETs using HMMs
Mobile ad-hoc networks (MANETs) present quite large packet loss bursts due to mobility. In this work we propose two models based on hidden Markov models for estimating packet arri...
Carlos Miguel Tavares Calafate, Pietro Manzoni, Ma...
ICPP
1996
IEEE
14 years 22 days ago
Restructuring Programs for High-Speed Computers with Polaris
The ability to automatically parallelize standard programming languages results in program portability across a wide range of machine architectures. It is the goal of the Polaris ...
William Blume, Rudolf Eigenmann, Keith Faigin, Joh...
FPL
2006
Springer
96views Hardware» more  FPL 2006»
14 years 7 days ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...
DICTA
2007
13 years 10 months ago
Speeding up Mutual Information Computation Using NVIDIA CUDA Hardware
We present an efficient method for mutual information (MI) computation between images (2D or 3D) for NVIDIA’s ‘compute unified device architecture’ (CUDA) compatible devic...
Ramtin Shams, Nick Barnes