Sciweavers

384 search results - page 64 / 77
» The Optimal Virtual Path Design of ATM Networks
Sort
View
TCAD
2008
92views more  TCAD 2008»
13 years 7 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
COMCOM
2006
168views more  COMCOM 2006»
13 years 7 months ago
Relay node placement in large scale wireless sensor networks
Scalability and extended lifetime are two critical design goals of any large scale wireless sensor network. A two-tiered network model has been proposed recently for this purpose....
Jian Tang, Bin Hao, Arunabha Sen
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
14 years 1 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
CN
2006
85views more  CN 2006»
13 years 7 months ago
A scalable and decentralized fast-rerouting scheme with efficient bandwidth sharing
This paper focuses on the protection of virtual circuits (Label Switched Paths, LSPs) in a (G)MPLS (Generalised Multi-Protocol Label Switching) network. The proposed algorithm is ...
Simon Balon, Laurent Mélon, Guy Leduc
MONET
2008
77views more  MONET 2008»
13 years 7 months ago
On Relay Node Placement and Assignment for Two-tiered Wireless Networks
Wireless networks that operate on batteries are imposed with energy constraints and long distance communications between nodes are not desirable. Implementing Relay Nodes (RNs) can...
Wenxuan Guo, Xin-Ming Huang, Wenjing Lou, Cao Lian...