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» The Primacy of Process Architecture
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SPAA
2000
ACM
14 years 26 days ago
Compact, multilayer layout for butterfly fat-tree
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...
André DeHon
DOOD
1995
Springer
124views Database» more  DOOD 1995»
14 years 26 days ago
Querying Semistructured Heterogeneous Information
Abstract. Semistructured data has no absolute schema xed in advance and its structure may be irregular or incomplete. Such data commonly arises in sources that do not impose a rigi...
Dallan Quass, Anand Rajaraman, Yehoshua Sagiv, Jef...
SIGCOMM
1995
ACM
14 years 25 days ago
Performance Analysis of MD5
MD5 is an authentication algorithm proposed as the required implementation of the authentication option in IPv6. This paper presents an analysis of the speed at which MD5 can be i...
Joseph D. Touch
CSO
2009
IEEE
14 years 17 days ago
Parallel Video Surveillance on the Multi-core Cell Broadband Engine
The IBM Cell Broadband Engine (BE) is a multicore processor with a PowerPC host processor (PPE) and 8 synergic processor engines (SPEs). The Cell BE architecture is designed to im...
Tamer F. Rabie, Hashir Karim Kidwai, Fadi N. Sibai
ICS
2010
Tsinghua U.
13 years 11 months ago
Speeding up Nek5000 with autotuning and specialization
Autotuning technology has emerged recently as a systematic process for evaluating alternative implementations of a computation, in order to select the best-performing solution for...
Jaewook Shin, Mary W. Hall, Jacqueline Chame, Chun...