10048 search results - page 169 / 2010 » The Structure and Performance of Interpreters |
125
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TIT
1998
15 years 4 months ago
1998
The paper introduces some generalizations of Vapnik’s method of structural risk minimisation (SRM). As well as making explicit some of the details on SRM, it provides a result t...
147
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MICRO
1997
IEEE
15 years 8 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
140
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ICIP
2006
IEEE
16 years 6 months ago
2006
IEEE
Multiplexed image reconstruction, estimating high resolution images from multiple low resolution images with highly overlapped fields of view, is improved when the magnification o...
128
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ICMCS
2005
IEEE
15 years 10 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
145
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EUROPAR
2005
Springer
15 years 10 months ago
2005
Springer
Sophisticated parallel matrix multiplication algorithms like PDGEMM exhibit a complex structure and can be controlled by a large set of parameters including blocking factors and bl...