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» The Throughput of Data Switches with and without Speedup
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TON
2008
124views more  TON 2008»
13 years 7 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown
IPPS
1998
IEEE
13 years 12 months ago
Design, Implementation and Evaluation of Parallel Pipelined STAP on Parallel Computers
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
Alok N. Choudhary, Wei-keng Liao, Donald Weiner, P...
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
13 years 12 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll
ASPLOS
2000
ACM
13 years 12 months ago
Architectural Support for Fast Symmetric-Key Cryptography
The emergence of the Internet as a trusted medium for commerce and communication has made cryptography an essential component of modern information systems. Cryptography provides ...
Jerome Burke, John McDonald, Todd M. Austin
EUROSYS
2007
ACM
14 years 4 months ago
Competitive prefetching for concurrent sequential I/O
During concurrent I/O workloads, sequential access to one I/O stream can be interrupted by accesses to other streams in the system. Frequent switching between multiple sequential ...
Chuanpeng Li, Kai Shen, Athanasios E. Papathanasio...