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» The Underlying Logic of Hoare Logic
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ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
PDP
2007
IEEE
14 years 1 months ago
Metadata Integration and Media Transcoding in Universal-Plug-and-Play (UPnP) Enabled Networks
Universal Plug and Play (UPnP) is a widely accepted standard for automatically detecting devices and services in a local area network as well as for describing and controlling the...
M. Jakab, Michael Kropfberger, M. Ofner, Roland Tu...
NCA
2007
IEEE
14 years 1 months ago
Towards IQ-Appliances: Quality-awareness in Information Virtualization
Our research addresses two important problems that arise in modern large-scale distributed systems: (1) the necessity to virtualize their data flows by applying actions such as ï...
Radhika Niranjan, Ada Gavrilovska, Karsten Schwan,...
EMSOFT
2007
Springer
14 years 1 months ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant
LPNMR
2007
Springer
14 years 1 months ago
A Common View on Strong, Uniform, and Other Notions of Equivalence in Answer-Set Programming
Logic programming under the answer-set semantics nowadays deals with numerous different notions of equivalence between programs. This is due to the fact that equivalence for substi...
Stefan Woltran