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» The WarpIV Simulation Kernel
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CASES
2001
ACM
15 years 6 months ago
A system-on-a-chip lock cache with task preemption support
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
USENIX
2008
15 years 5 months ago
Prefetching with Adaptive Cache Culling for Striped Disk Arrays
Conventional prefetching schemes regard prediction accuracy as important because useless data prefetched by a faulty prediction may pollute the cache. If prefetching requires cons...
Sung Hoon Baek, Kyu Ho Park
CASES
2005
ACM
15 years 5 months ago
SECA: security-enhanced communication architecture
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...
USENIX
1994
15 years 4 months ago
A Better Update Policy
y-filled data block results in a delayed write,Abstract while a modification that fills a block results in an immediate, although asynchronous, write. TheSome file systems can dela...
Jeffrey C. Mogul
BMCBI
2010
135views more  BMCBI 2010»
15 years 3 months ago
Detecting disease associated modules and prioritizing active genes based on high throughput data
Background: The accumulation of high-throughput data greatly promotes computational investigation of gene function in the context of complex biological systems. However, a biologi...
Yu-Qing Qiu, Shi-Hua Zhang, Xiang-Sun Zhang, Luona...