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ACMMSP
2006
ACM
247views Hardware» more  ACMMSP 2006»
14 years 1 months ago
A flexible data to L2 cache mapping approach for future multicore processors
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
Lei Jin, Hyunjin Lee, Sangyeun Cho
FPL
2005
Springer
140views Hardware» more  FPL 2005»
14 years 1 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
CORR
2006
Springer
100views Education» more  CORR 2006»
13 years 7 months ago
Bilayer Low-Density Parity-Check Codes for Decode-and-Forward in Relay Channels
This paper describes an efficient implementation of binning for decode-and-forward (DF) in relay channels using lowdensity parity-check (LDPC) codes. Bilayer LDPC codes are devised...
Peyman Razaghi, Wei Yu
JCST
2008
134views more  JCST 2008»
13 years 7 months ago
Orthogonal Methods Based Ant Colony Search for Solving Continuous Optimization Problems
Research into ant colony algorithms for solving continuous optimization problems forms one of the most significant and promising areas in swarm computation. Although traditional an...
Xiaomin Hu, Jun Zhang, Yun Li
ML
2007
ACM
156views Machine Learning» more  ML 2007»
13 years 7 months ago
Active learning for logistic regression: an evaluation
Which active learning methods can we expect to yield good performance in learning binary and multi-category logistic regression classifiers? Addressing this question is a natural ...
Andrew I. Schein, Lyle H. Ungar