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FCCM
2006
IEEE
195views VLSI» more  FCCM 2006»
14 years 3 months ago
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
Andrey Bogdanov, M. C. Mertens
ERSA
2003
137views Hardware» more  ERSA 2003»
13 years 11 months ago
Next Generation Architecture for Heterogeneous Embedded Systems
The Software Communications Architecture (SCA), a mandatory specification for Software Radio implementations by the Joint Tactical Radio System (JTRS), defines a Common Object R...
S. Murat Bicer, Frank Pilhofer, Graham Bardouleau,...
DAC
2006
ACM
14 years 10 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
14 years 4 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...
ANCS
2008
ACM
13 years 11 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu