862 search results - page 169 / 173 » The amorphous FPGA architecture |
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
SASP
2008
IEEE
14 years 1 months ago
2008
IEEE
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
CF
2010
ACM
14 years 13 days ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
NIXDORF
1992
13 years 11 months ago
1992
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...