1994 search results - page 26 / 399 » The design of a high performance low power microprocessor |
HAPTICS
2005
IEEE
14 years 2 months ago
2005
IEEE
We built a high fidelity, low mass, linear haptic display, with a peak force output of 8.5 Newtons,
HPCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
ITC
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
CODES
2004
IEEE
14 years 14 days ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...