A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wideissue, highly speculative cores. Microarchitectural speculation...
Karthik Natarajan, Heather Hanson, Stephen W. Keck...
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...