Sciweavers

1994 search results - page 35 / 399
» The design of a high performance low power microprocessor
Sort
View
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
14 years 1 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
ICCD
2006
IEEE
77views Hardware» more  ICCD 2006»
14 years 5 months ago
Iterative-Constructive Standard Cell Placer for High Speed and Low Power
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
Sungjae Kim, Eugene Shragowitz
IJRR
2006
171views more  IJRR 2006»
13 years 8 months ago
The Cobotic Hand Controller: Design, Control and Performance of a Novel Haptic Display
We examine the design, control and performance of the Cobotic Hand Controller, a novel, six-degree-of-freedom, admittance controlled haptic display. A highly geared admittance arch...
Eric L. Faulring, J. Edward Colgate, Michael A. Pe...
HOTI
2005
IEEE
14 years 2 months ago
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
A partitioned TCAM-based search engine is presented that increases packet forwarding rate multiple times over traditional TCAMs. The model works for IPv4 and IPv6 packet forwardin...
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Pa...
ANCS
2008
ACM
13 years 10 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu