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» The design of a high performance low power microprocessor
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JCP
2008
232views more  JCP 2008»
13 years 8 months ago
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper...
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira ...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
NOCS
2008
IEEE
14 years 3 months ago
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang,...
VLSID
2001
IEEE
169views VLSI» more  VLSID 2001»
14 years 9 months ago
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, ...
MOBIHOC
2005
ACM
14 years 8 months ago
Temporal properties of low power wireless links: modeling and implications on multi-hop routing
Recently, several studies have analyzed the statistical properties of low power wireless links in real environments, clearly demonstrating the differences between experimentally o...
Alberto Cerpa, Jennifer L. Wong, Miodrag Potkonjak...