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» The design of a high performance low power microprocessor
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ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 1 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
ETT
2007
99views Education» more  ETT 2007»
13 years 8 months ago
On the design of rate-compatible serially concatenated convolutional codes
A powerful class of rate-compatible serially concatenated convolutional codes (SCCCs) has been proposed based on minimizing analytical upper bounds on the error probability in the ...
Alexandre Graell i Amat, Fredrik Brännstr&oum...
GLOBECOM
2007
IEEE
14 years 3 months ago
MIMO-OFDM Channel Estimation in Presence of Carrier Frequency Offsets
— Optimal pilot design and placement for channel estimation in Multiple-input Multiple-output (MIMO) Orthogonal Frequency-Division Multiplexing (OFDM) systems in the presence of ...
Zhongshan Zhang, Wei Zhang, Chintha Tellambura
EH
2004
IEEE
117views Hardware» more  EH 2004»
14 years 19 days ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
CF
2005
ACM
13 years 11 months ago
Exploiting temporal locality in drowsy cache policies
Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage ...
Salvador Petit, Julio Sahuquillo, Jose M. Such, Da...