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» The design of a high performance low power microprocessor
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IPPS
2007
IEEE
14 years 3 months ago
Scaling and Packing on a Chip Multiprocessor
Power management is critical in server and high-performancecomputing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support ...
Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Raw...
HPCA
2006
IEEE
14 years 9 months ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...
TDSC
2010
111views more  TDSC 2010»
13 years 7 months ago
Using Underutilized CPU Resources to Enhance Its Reliability
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Sur...
IPPS
1998
IEEE
14 years 1 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 3 months ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco