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EUROPAR
2001
Springer
14 years 1 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
SIGGRAPH
2010
ACM
14 years 1 months ago
Sampling-based contact-rich motion control
Human motions are the product of internal and external forces, but these forces are very difficult to measure in a general setting. Given a motion capture trajectory, we propose ...
Libin Liu, KangKang Yin, Michiel van de Panne, Tia...
ICC
2000
IEEE
123views Communications» more  ICC 2000»
14 years 1 months ago
A Per-Flow Based Node Architecture for Integrated Services Packet Networks
As the Internet transforms from the traditional best-effort service network into QoS-capable multi-service network, it is essential to have new architectural design and appropriate...
Dapeng Wu, Yiwei Thomas Hou, Takeo Hamada, Zhi-Li ...
ICNP
2000
IEEE
14 years 1 months ago
Generalized Load Sharing for Packet-Switching Networks
—In this paper, we extend the load sharing framework to study how to effectively perform flow-based traffic splitting in multipath communication networks. The generalized load sh...
Ka-Cheong Leung, Victor O. K. Li
ICPPW
2000
IEEE
14 years 1 months ago
Reducing Web Latency with Hierarchical Cache-Based Prefetching
Proxy caches have become a central mechanism for reducing the latency of web document retrieval. While caching alone reduces latency for previously requested documents, web docume...
Dan Foygel, Dennis Strelow