Sciweavers

7271 search results - page 1264 / 1455
» The high performance storage system
Sort
View
VLSID
2001
IEEE
144views VLSI» more  VLSID 2001»
14 years 9 months ago
Next Generation Network Processors
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
Deepak Kataria
MOBISYS
2008
ACM
14 years 9 months ago
SeeMon: scalable and energy-efficient context monitoring framework for sensor-rich mobile environments
Proactively providing services to mobile individuals is essential for emerging ubiquitous applications. The major challenge in providing users with proactive services lies in cont...
Seungwoo Kang, Jinwon Lee, Hyukjae Jang, Hyonik Le...
IROS
2008
IEEE
250views Robotics» more  IROS 2008»
14 years 3 months ago
Mobile robot broadband sound localisation using a biologically inspired spiking neural network
— A biologically inspired azimuthal broadband sound localisation system is introduced to simulates the functional organisation of the human auditory midbrain up to the inferior c...
Jindong Liu, Harry R. Erwin, Stefan Wermter
MICRO
2007
IEEE
159views Hardware» more  MICRO 2007»
14 years 3 months ago
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
Kypros Constantinides, Onur Mutlu, Todd M. Austin,...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
14 years 3 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
« Prev « First page 1264 / 1455 Last » Next »