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PCI
2005
Springer
15 years 8 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
CP
2004
Springer
15 years 8 months ago
Leveraging the Learning Power of Examples in Automated Constraint Acquisition
Constraint programming is rapidly becoming the technology of choice for modeling and solving complex combinatorial problems. However, users of constraint programming technology nee...
Christian Bessière, Remi Coletta, Eugene C....
SDMW
2004
Springer
15 years 8 months ago
Experimental Analysis of Privacy-Preserving Statistics Computation
The recent investigation of privacy-preserving data mining and other kinds of privacy-preserving distributed computation has been motivated by the growing concern about the privacy...
Hiranmayee Subramaniam, Rebecca N. Wright, Zhiqian...
ICNP
2003
IEEE
15 years 8 months ago
The Impact of False Sharing on Shared Congestion Management
Several recent proposals for sharing congestion information across concurrent flows between end-systems overlook an important problem: two or more flows sharing congestion state...
Aditya Akella, Srinivasan Seshan, Hari Balakrishna...
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ICPP
2003
IEEE
15 years 8 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...