Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
This paper presents a formal approach to threat-driven modeling and verification of secure software using aspect-oriented Petri nets. Based on the behavior model of intended funct...
Abstract. SafeGen is a meta-programming language for writing statically safe generators of Java programs. If a program generator written in SafeGen passes the checks of the SafeGen...
Safety is increasingly important for software based, critical systems. Fault tree analysis (FTA) is a safety technique from engineering, developed for analyzing and assessing syste...
We study a clock synchronization protocol for the Chess WSN. First, we model the protocol as a network of timed automata and verify various instances using the Uppaal model checker...
Faranak Heidarian, Julien Schmaltz, Frits W. Vaand...