Sciweavers

3600 search results - page 703 / 720
» The settling-time reducibility ordering
Sort
View
JPDC
2007
60views more  JPDC 2007»
13 years 7 months ago
The impact of wrong-path memory references in cache-coherent multiprocessor systems
The core of current-generation high-performance multiprocessor systems is out-of-order execution processors with aggressive branch prediction. Despite their relatively high branch...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
TSP
2008
87views more  TSP 2008»
13 years 7 months ago
Interference Suppression for Memoryless Nonlinear Multiuser Systems Using Constellation Structure
A generalized concept of interference suppression is introduced for multiuser systems with a known memoryless transmit non-linearity, such as in the downlink amplifier of a satelli...
Ananya Sen Gupta, Andrew Singer
TVLSI
2008
157views more  TVLSI 2008»
13 years 7 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
TWC
2008
154views more  TWC 2008»
13 years 7 months ago
MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks
Abstract-- In many portable devices, wireless network interfaces consume upwards of 30% of scarce system energy. Reducing the transceiver's power consumption to extend the sys...
Sofie Pollin, Rahul Mangharam, Bruno Bougard, Lies...
TWC
2008
120views more  TWC 2008»
13 years 7 months ago
Binary Power Control for Sum Rate Maximization over Multiple Interfering Links
We consider allocating the transmit powers for a wireless multi-link (N-link) system, in order to maximize the total system throughput under interference and noise impairments, and...
Anders Gjendemsjø, David Gesbert, Geir E. &...