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» The use of random simulation in formal verification
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MEMOCODE
2003
IEEE
14 years 27 days ago
Bridging CSP and C++ with Selective Formalism and Executable Specifications
CSP (Communicating Sequential Processes) is a useful algebraic notation for creating a hierarchical behavioural specification for concurrent systems, due to its formal interproces...
William B. Gardner
ASM
2010
ASM
14 years 23 days ago
Formal Probabilistic Analysis: A Higher-Order Logic Based Approach
Traditionally, simulation is used to perform probabilistic analysis. However, it provides less accurate results and cannot handle large-scale problems due to the enormous CPU time ...
Osman Hasan, Sofiène Tahar
UML
2001
Springer
14 years 2 days ago
Formalization of UML-Statecharts
The work presented here is part of a project that aims at the definition of a methodology for developing realtime software systems based on UML. In fact, being relatively easy to ...
Michael von der Beeck
IJNSEC
2007
121views more  IJNSEC 2007»
13 years 7 months ago
Injecting Heterogeneity Through Protocol Randomization
In this paper, we argue that heterogeneity should be an important principle in design and use of cryptographic protocols. We use automated formal analysis tools to randomly genera...
Li Zhuang, J. D. Tygar, Rachna Dhamija
CAISE
2006
Springer
13 years 11 months ago
A Method for Functional Alignment Verification in Hierarchical Enterprise Models
Enterprise modeling involves multiple domains of expertise: requirements engineering, business process modeling, IT development etc. Our experience has shown that hierarchical ente...
Irina Rychkova, Alain Wegmann