Sciweavers

145 search results - page 18 / 29
» The use of random simulation in formal verification
Sort
View
EPK
2006
114views Management» more  EPK 2006»
13 years 9 months ago
Verifying Properties of (Timed) Event Driven Process Chains by Transformation to Hybrid Automata
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
Stefan Denne
TPHOL
1998
IEEE
13 years 12 months ago
Program Abstraction in a Higher-Order Logic Framework
Abstraction in a Higher-Order Logic Framework Marco Benini Sara Kalvala Dirk Nowotka Department of Computer Science University of Warwick, Coventry, CV4 7AL, United Kingdom We pres...
Marco Benini, Sara Kalvala, Dirk Nowotka
APN
2008
Springer
13 years 9 months ago
Modeling and Analysis of Security Protocols Using Role Based Specifications and Petri Nets
Abstract. In this paper, we introduce a framework composed of a syntax and its compositional Petri net semantics, for the specification and verification of properties (like authent...
Roland Bouroulet, Raymond R. Devillers, Hanna Klau...
CAV
2009
Springer
157views Hardware» more  CAV 2009»
14 years 8 months ago
Explaining Counterexamples Using Causality
Abstract. When a model does not satisfy a given specification, a counterexample is produced by the model checker to demonstrate the failure. A user must then examine the counterexa...
Ilan Beer, Shoham Ben-David, Hana Chockler, Avigai...
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
13 years 7 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...