145 search results - page 7 / 29 » The use of random simulation in formal verification |
DFG
2004
Springer
14 years 1 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
AINA
2003
IEEE
14 years 1 months ago
2003
IEEE
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
PERCOM
2010
ACM
13 years 7 months ago
2010
ACM
In autonomic networks, the self-configuration of network entities is one of the most desirable properties. In this paper, we show how formal verification techniques can verify the ...
ICFEM
1998
Springer
14 years 2 months ago
1998
Springer
Studying industrial systems by simulation enables the designer to study the dynamic behaviour and to determine some characteristics of the system. Unfortunately, simulation also h...
DAC
2005
ACM
13 years 12 months ago
2005
ACM
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...