Sciweavers

32 search results - page 7 / 7
» Thumbnail rectilinear Steiner trees
Sort
View
TCAD
2002
93views more  TCAD 2002»
13 years 10 months ago
Hierarchical buffered routing tree generation
Abstract--This paper presents a solution to the problem of performance-driven buffered routing tree generation for VLSI circuits. Using a novel bottom-up construction algorithm and...
Amir H. Salek, Jinan Lou, Massoud Pedram
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
14 years 26 days ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen