26 search results - page 4 / 6 » Tiling Imperfectly-Nested Loop Nests |
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...
ICS
2000
Tsinghua U.
13 years 11 months ago
2000
Tsinghua U.
We present an approach for synthesizing transformations to enhance locality in imperfectly-nested loops. The key idea is to embed the iteration space of every statement in a loop ...
ICPP
1996
IEEE
13 years 11 months ago
1996
IEEE
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
EUROPAR
1999
Springer
13 years 11 months ago
1999
Springer
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Du...
PCI
2005
Springer
14 years 28 days ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...