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» Tilings as a programming exercise
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LCPC
2004
Springer
14 years 3 months ago
Implementation of Parallel Numerical Algorithms Using Hierarchically Tiled Arrays
In this paper, we describe our experience in writing parallel numerical algorithms using Hierarchically Tiled Arrays (HTAs). HTAs are classes of objects that encapsulate parallelis...
Ganesh Bikshandi, Basilio B. Fraguela, Jia Guo, Ma...
MTPP
2010
13 years 4 months ago
Parallelization of Motion JPEG Decoder on TILE64 Many-Core Platform
The ubiquity of many-core architectures poses challenges to software developers to make scalable software. To parallelize data-intensive applications on a many-core platform, one h...
Xuan-Yi Lin, Chung-Yu Huang, Pei-Man Yang, Tai-Wen...
PCI
2005
Springer
14 years 3 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
EGH
2004
Springer
14 years 3 months ago
Tile-based texture mapping on graphics hardware
Texture mapping has been a fundamental feature for commodity graphics hardware. However, a key challenge for texture mapping is how to store and manage large textures on graphics ...
Li-Yi Wei
STOC
2001
ACM
115views Algorithms» more  STOC 2001»
14 years 10 months ago
Running time and program size for self-assembled squares
Recently Rothemund and Winfree 6] have considered the program size complexity of constructing squares by selfassembly. Here, we consider the time complexity of such constructions ...
Leonard M. Adleman, Qi Cheng, Ashish Goel, Ming-De...