Sciweavers

6111 search results - page 1106 / 1223
» Time, Hardware, and Uniformity
Sort
View
ICS
2003
Tsinghua U.
14 years 3 months ago
Enhancing memory level parallelism via recovery-free value prediction
—The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow me...
Huiyang Zhou, Thomas M. Conte
EUROMICRO
2002
IEEE
14 years 3 months ago
Performance Tradeoffs for Static Allocation of Zero-Copy Buffers
Internet services like the world-wide web and multimedia applications like News- and Video-on-Demand have become very popular over the last years. Due to the large number of users ...
Pål Halvorsen, Espen Jorde, Karl-André...
FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
14 years 3 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
IEEEPACT
2002
IEEE
14 years 3 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
14 years 3 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
« Prev « First page 1106 / 1223 Last » Next »