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ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
14 years 16 days ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
ICONS
2008
IEEE
14 years 3 months ago
An Efficient Hardware Implementation of the Tate Pairing in Characteristic Three
DL systems with bilinear structure recently became an important base for cryptographic protocols such as identity-based encryption (IBE). Since the main computational task is the ...
Giray Kömürcü, Erkay Savas
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 10 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
ESTIMEDIA
2003
Springer
14 years 2 months ago
Improving Performance and Quality thru Hardware Reconfiguration: Potentials and Adaptive Object Tracking Case Study
Reconfigurable hardware devices are envisioned as the proper platform to implement multimedia applications, providing both real time performance and dynamic adaptability for the a...
Soheil Ghiasi, Hyun J. Moon, Majid Sarrafzadeh
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
14 years 26 days ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich