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ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
12 years 10 days ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
EMSOFT
2009
Springer
14 years 4 months ago
Cache-aware scheduling and analysis for multicores
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu
WORDS
2005
IEEE
14 years 3 months ago
A Framework for Preparing Experimental Evaluation of Rerouting Mechanisms
Since the deployment of real-time sensitive applications in the Internet, the research community has been struggling to leverage the IP best-effort networks for providing QoS assu...
Reinaldo de Barros Correia, Luiz F. Rust da Costa ...
RTSS
1999
IEEE
14 years 2 months ago
Design and Implementation of Statistical Rate Monotonic Scheduling in KURT Linux
Statistical Rate Monotonic Scheduling (SRMS) is a generalization of the classical RMS results of Liu and Layland [LL73] for periodic tasks with highly variable execution times and...
Alia Atlas, Azer Bestavros
INFOCOM
2010
IEEE
13 years 8 months ago
Joint Power and Secret Key Queue Management for Delay Limited Secure Communication
—In recent years, the famous wiretap channel has been revisited by many researchers and information theoretic secrecy has become an active area of research in this setting. In th...
Onur Güngör 0002, Jian Tan, Can Emre Kok...