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» Time Management in The High Level Architecture
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HPCA
2005
IEEE
14 years 2 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
NOMS
2008
IEEE
134views Communications» more  NOMS 2008»
14 years 3 months ago
Manageability design for an autonomic management of semi-dynamic web service compositions
Abstract—Web service compositions (WSC), as part of a serviceoriented architecture (SOA), have to be managed to ensure compliance with guaranteed service levels. In this context,...
Christof Momm, I. P. Hallerbach, Sebastian Abeck, ...
MSS
2005
IEEE
175views Hardware» more  MSS 2005»
14 years 2 months ago
High Performance Storage System Scalability: Architecture, Implementation and Experience
The High Performance Storage System (HPSS) provides scalable hierarchical storage management (HSM), archive, and file system services. Its design, implementation and current domin...
Richard W. Watson
RTCSA
2007
IEEE
14 years 2 months ago
MB++: An Integrated Architecture for Pervasive Computing and High-Performance Computing
MB++ is a system that caters to the dynamic needs of applications in a distributed, pervasive computing environment that has a wide variety of devices that act as producers and co...
David J. Lillethun, David Hilley, Seth Horrigan, U...
ICC
2007
IEEE
127views Communications» more  ICC 2007»
14 years 2 months ago
A Memory Unit for Priority Management in IPSec Accelerators
— This paper introduces a hardware architecture for high speed network processors, focusing on support for Quality of Service in IPSec-dedicated systems. The effort is aimed at d...
Luigi Dadda, Alberto Ferrante, Marco Macchetti