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» Time Management in The High Level Architecture
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HICSS
2003
IEEE
148views Biometrics» more  HICSS 2003»
14 years 1 months ago
Managing Multimedia Traffic in IP Integrated over Differentiated Services: SIP dynamic signaling inter-working
The current IETF standardization work has highlighted the feasibility of providing the users with a QoS network architecture in the framework of Integrated Services over Different...
Stefano Giordano, M. Mancino, A. Martucci, Saverio...
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 6 days ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 5 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
CIKM
2008
Springer
13 years 10 months ago
Achieving both high precision and high recall in near-duplicate detection
To find near-duplicate documents, fingerprint-based paradigms such as Broder's shingling and Charikar's simhash algorithms have been recognized as effective approaches a...
Lian'en Huang, Lei Wang, Xiaoming Li
CIDR
2003
121views Algorithms» more  CIDR 2003»
13 years 10 months ago
Towards High Performance Peer-to-Peer Content and Resource Sharing Systems
Peer-to-peer sharing systems are becoming increasingly popular and an exciting new class of innovative, internet-based data management systems. In these systems, users contribute ...
Peter Triantafillou, Chryssani Xiruhaki, Manolis K...