652 search results - page 31 / 131 » Time Management in The High Level Architecture |
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
SIES
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--In distributed embedded systems operated by battery, energy management is a critical issue that has to be addressed at different architecture levels. For systems that tig...
IPPS
2009
IEEE
14 years 3 months ago
2009
IEEE
In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
ASYNC
1997
IEEE
14 years 7 days ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...