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» Time Management in The High Level Architecture
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ICPP
2009
IEEE
14 years 3 months ago
Mapping the FDTD Application to Many-Core Chip Architectures
—This paper reports a study of mapping the Finite Difference Time Domain (FDTD) application to the IBM Cyclops64 (C64) many-core chip architecture [1]. C64 is chosen for this stu...
Daniel Orozco, Guang R. Gao
CERA
2010
105views more  CERA 2010»
13 years 8 months ago
Implications of Alternative Multilevel Design Methods for Design Process Management
Multilevel design problems are typically decomposed into a hierarchy of distributed and strongly coupled sub-problems, each solved by design teams with specialized knowledge and t...
David Shahan, Carolyn Seepersad Seepersad
HIPC
2009
Springer
13 years 6 months ago
Highly scalable algorithm for distributed real-time text indexing
Stream computing research is moving from terascale to petascale levels. It aims to rapidly analyze data as it streams in from many sources and make decisions with high speed and a...
Ankur Narang, Vikas Agarwal, Monu Kedia, Vijay K. ...
IM
2003
13 years 10 months ago
Performance Management for Cluster Based Web Services
: We present an architecture and prototype implementation of a performance management system for cluster-based web services. The system supports multiple classes of web services tr...
Ronald M. Levy, Jay Nagarajarao, Giovanni Pacifici...
ICASSP
2011
IEEE
13 years 11 days ago
A high throughput parallel AVC/H.264 context-based adaptive binary arithmetic decoder
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
Jia-Wei Liang, He-Yuan Lin, Gwo Giun Lee