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» Time Management in The High Level Architecture
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DATE
1999
IEEE
172views Hardware» more  DATE 1999»
14 years 1 months ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez
ISARCS
2010
240views Hardware» more  ISARCS 2010»
13 years 10 months ago
Engineering a Distributed e-Voting System Architecture: Meeting Critical Requirements
Voting is a critical component of any democratic process; and electronic voting systems should be developed following best practices for critical system development. E-voting has i...
J. Paul Gibson, Eric Lallet, Jean-Luc Raffy
TMC
2008
159views more  TMC 2008»
13 years 7 months ago
Protecting Location Privacy with Personalized k-Anonymity: Architecture and Algorithms
Continued advances in mobile networks and positioning technologies have created a strong market push for location-based applications. Examples include location-aware emergency resp...
Bugra Gedik, Ling Liu
ANCS
2011
ACM
12 years 8 months ago
A Scalability Study of Enterprise Network Architectures
The largest enterprise networks already contain hundreds of thousands of hosts. Enterprise networks are composed of Ethernet subnets interconnected by IP routers. These routers re...
Brent Stephens, Alan L. Cox, Scott Rixner, T. S. E...
DAC
2012
ACM
11 years 11 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...