652 search results - page 94 / 131 » Time Management in The High Level Architecture |
DAC
1999
ACM
14 years 1 months ago
1999
ACM
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
SEMWEB
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. Increasingly huge RDF data sets are being published on the Web. Currently, they use different syntaxes of RDF, contain high levels of redundancy and have a plain indivisi...
ICCAD
2006
IEEE
14 years 5 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
We present an efficient technique for finding the mean and variance of the full-chip leakage of a candidate design, while considering logic-structures and both die-to-die and with...