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ICDCS
2009
IEEE
14 years 4 months ago
On the Utility of Inference Mechanisms
A number of network path delay, loss, or bandwidth inference mechanisms have been proposed over the past decade. Concurrently, several network measurement services have been deplo...
Ethan Blanton, Sonia Fahmy, Greg N. Frederickson
EUROSYS
2007
ACM
14 years 4 months ago
Tashkent+: memory-aware load balancing and update filtering in replicated databases
We present a memory-aware load balancing (MALB) technique to dispatch transactions to replicas in a replicated database. Our MALB algorithm exploits knowledge of the working sets ...
Sameh Elnikety, Steven G. Dropsho, Willy Zwaenepoe...
EUROGRAPHICS
2010
Eurographics
14 years 4 months ago
Adding Depth to Cartoons Using Sparse Depth (In)equalities
This paper presents a novel interactive approach for adding depth information into hand-drawn cartoon images and animations. In comparison to previous depth assignment techniques ...
Daniel Sýkora, David Sedlacek, Sun Jinchao, John ...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson