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ASPDAC
2006
ACM
128views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A new test and characterization scheme for 10+ GHz low jitter wide band PLL
- This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We me...
Kazuhiko Miki, David Boerstler, Eskinder Hailu, Ji...
ICMLA
2004
13 years 11 months ago
Planning with predictive state representations
Predictive state representation (PSR) models for controlled dynamical systems have recently been proposed as an alternative to traditional models such as partially observable Mark...
Michael R. James, Satinder P. Singh, Michael L. Li...
IEEEPACT
2005
IEEE
14 years 3 months ago
Extended Whole Program Paths
We describe the design, generation and compression of the extended whole program path (eWPP) representation that not only captures the control flow history of a program execution...
Sriraman Tallam, Rajiv Gupta, Xiangyu Zhang
NOMS
2008
IEEE
14 years 4 months ago
Tracking back the root cause of a path change in interdomain routing
—Interdomain routes change over time, and it is impressive to observe up to which extent. Routes may change many times in the same day and sometimes in the same hour or minute. S...
Alessio Campisano, Luca Cittadini, Giuseppe Di Bat...
ARCS
2005
Springer
14 years 3 months ago
Reusable Design of Inter-chip Communication Interfaces for Next Generation of Adaptive Computing Systems
Abstract. The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and ...
Vincent Kotzsch, Jörg Schneider, Günther...