Sciweavers

4306 search results - page 166 / 862
» Timed Testing with TorX
Sort
View
HCI
2009
13 years 8 months ago
Estimating Productivity: Composite Operators for Keystroke Level Modeling
Task time is a measure of productivity in an interface. Keystroke Level Modeling (KLM) can predict experienced user task time to within 10 to 30% of actual times. One of the bigges...
Jeff Sauro
ICCD
2004
IEEE
172views Hardware» more  ICCD 2004»
14 years 7 months ago
A Signal Integrity Test Bed for PCB Buses
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
Jihong Ren, Mark R. Greenstreet
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
14 years 4 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
SEFM
2005
IEEE
14 years 4 months ago
Experimental Evaluation of FSM-Based Testing Methods
The development of test cases is an important issue for testing software, communication protocols and other reactive systems. A number of methods are known for the development of ...
Rita Dorofeeva, Nina Yevtushenko, Khaled El-Fakih,...
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
14 years 3 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...