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ATS
2004
IEEE
93views Hardware» more  ATS 2004»
13 years 11 months ago
Hybrid BIST Test Scheduling Based on Defect Probabilities
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
GLVLSI
2002
IEEE
98views VLSI» more  GLVLSI 2002»
14 years 14 days ago
Minimizing concurrent test time in SoC's by balancing resource usage
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
Dan Zhao, Shambhu J. Upadhyaya, Martin Margala
APN
2005
Springer
13 years 9 months ago
Timed-Arc Petri Nets vs. Networks of Timed Automata
Abstract. We establish mutual translations between the classes of 1safe timed-arc Petri nets (and its extension with testing arcs) and networks of timed automata (and its subclass ...
Jirí Srba
IPPS
1997
IEEE
13 years 11 months ago
Time-Stamping Algorithms for Parallelization of Loops at Run-Time
In this paper, we present two new run-time algorithms for the parallelization of loops that have indirect access patterns. The algorithms can handle any type of loop-carried depen...
Cheng-Zhong Xu, Vipin Chaudhary
ITC
1996
IEEE
98views Hardware» more  ITC 1996»
13 years 11 months ago
Mixed-Mode BIST Using Embedded Processors
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre...