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DELTA
2004
IEEE
13 years 11 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
TSMC
2008
94views more  TSMC 2008»
13 years 7 months ago
Test Sequencing in Complex Manufacturing Systems
Testing complex manufacturing systems, such as an ASML [1] lithographic machine, takes up to 45% of the total development time of a system. The problem of which tests must be execu...
R. Boumen, I. S. M. de Jong, J. W. H. Vermunt, J. ...
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
13 years 11 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
ECBS
2010
IEEE
230views Hardware» more  ECBS 2010»
13 years 11 months ago
A Model-Based Regression Testing Approach for Evolving Software Systems with Flexible Tool Support
Model-based selective regression testing promises reduction in cost and labour by selecting a subset of the test suite corresponding to the modifications after system evolution. H...
Qurat-ul-ann Farooq, Muhammad Zohaib Z. Iqbal, Zaf...
ATS
2001
IEEE
172views Hardware» more  ATS 2001»
13 years 11 months ago
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters
Testing and diagnosis are important issues in system-onchip (SOC) development, as more and more embedded cores are being integrated into the chips. In this paper we propose a buil...
Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih...