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DAC
2009
ACM
14 years 10 months ago
Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...
Himanshu Jain, Edmund M. Clarke
ICML
2005
IEEE
14 years 10 months ago
Q-learning of sequential attention for visual object recognition from informative local descriptors
This work provides a framework for learning sequential attention in real-world visual object recognition, using an architecture of three processing stages. The first stage rejects...
Lucas Paletta, Gerald Fritz, Christin Seifert
CP
2009
Springer
14 years 10 months ago
Confidence-Based Work Stealing in Parallel Constraint Programming
The most popular architecture for parallel search is work stealing: threads that have run out of work (nodes to be searched) steal from threads that still have work. Work stealing ...
Geoffrey Chu, Christian Schulte, Peter J. Stuckey
HPCA
2009
IEEE
14 years 10 months ago
Elastic-buffer flow control for on-chip networks
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel b...
George Michelogiannakis, James D. Balfour, William...
VLSID
2005
IEEE
128views VLSI» more  VLSID 2005»
14 years 10 months ago
On-Line Synthesis for Partially Reconfigurable FPGAs
An important application of dynamically and partially reconfigurable computing platforms is in dynamic task allocation and execution. On-line synthesis, on-line placement and on-l...
Renqiu Huang, Ranga Vemuri