Sciweavers

483 search results - page 53 / 97
» Timing Games and Shared Memory
Sort
View
146
Voted
IPPS
1999
IEEE
15 years 7 months ago
Reducing I/O Complexity by Simulating Coarse Grained Parallel Algorithms
Block-wise access to data is a central theme in the design of efficient external memory (EM) algorithms. A second important issue, when more than one disk is present, is fully par...
Frank K. H. A. Dehne, David A. Hutchinson, Anil Ma...
150
Voted
HIPC
2004
Springer
15 years 9 months ago
Lock-Free Parallel Algorithms: An Experimental Study
Abstract. Lock-free shared data structures in the setting of distributed computing have received a fair amount of attention. Major motivations of lock-free data structures include ...
Guojing Cong, David A. Bader
IEEEPACT
2008
IEEE
15 years 10 months ago
Distributed cooperative caching
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is...
Enric Herrero, José González, Ramon ...
150
Voted
DSD
2007
IEEE
142views Hardware» more  DSD 2007»
15 years 10 months ago
Decoupling of Computation and Communication with a Communication Assist
Abstract. In an embedded multiprocessor system the minimum throughput and maximum latency of real-time applications are usually derived given the worst-case execution time of the s...
Arno Moonen, Marco Bekooij, Rene van den Berg, Jef...
SIAMCOMP
1998
117views more  SIAMCOMP 1998»
15 years 3 months ago
The Queue-Read Queue-Write PRAM Model: Accounting for Contention in Parallel Algorithms
This paper introduces the queue-read, queue-write (qrqw) parallel random access machine (pram) model, which permits concurrent reading and writing to shared memory locations, but ...
Phillip B. Gibbons, Yossi Matias, Vijaya Ramachand...